High performance integrated circuit (IC) devices include processing capabilities that require complex IC designs. While a high-level schematic of the IC device design may be developed on any available design platform, the implementation of this schematic to generate a functional layout for the IC device often results in complications that can affect the very capabilities for which the IC device has been developed. To avoid such problems, designers implement various checking tools, e.g., design rule checking (DRC) tools, to ensure the manufacturability of a layout that corresponds to these high-level schematics. In particular, a DRC tool is used to determine if an IC layout adheres to one or more of the complex technology ground rules necessary for successful production of the proposed IC device.
Although the checking tools provide some safeguards necessary for manufacturing, it is generally understood that they may not recognize unintentionally forward-biased diode devices. In general, a forward-biased diode device can occur in IC devices that include transitioning between voltage domains, self-biased P-wells and N-wells, and gate tie downs. In general, a gate tie down is intended to be a reverse-biased diode that protects the gate during manufacturing. In one example, a gate tie down is a P+ diffusion in an N-well. In another example, a gate tie down is a N+ diffusion in a P-well. However, if a P+ gate tie down diffusion is placed in an N-well that is tied to a lower voltage potential than the node driving the associated gate, then an unintentionally forward-biased diode device may result.
As mentioned above, any deficiency in the checking tools used to verify the integrity of an IC layout is significant. When translated to production layouts and eventual manufactured devices, most IC devices require complicated schematic layouts that result in forward-biased and parasitic diode devices unintentionally forming. Accordingly, to truly ascertain whether an IC device will function properly, designers should implement additional methods to verify the quality of the IC device design. Most of the methods employed, however, require a comprehensive suite of input patterns and other manually meticulous diagnostic schemes that are susceptible to, e.g., human error. Moreover, even if a designer develops a truly exhaustive method, the time required to verify a complicated IC design is very prohibitive. For these reasons, designers and manufacturers of IC devices would welcome a method that improves the likelihood of identifying forward-biased diodes, reduces the manual interaction of the designer, and enhances the productivity associated with implementing checking tools.